1. Field of the Invention
The present invention relates generally to a one-transistor (hereinafter referred to as ‘1T’) floating-body DRAM cell device with a non-volatile function, and, more particularly, to a 1T floating-body DRAM cell device that can improve device performance and characteristic distribution by providing an operation method having a non-volatile function to an 1T floating-body DRAM cell device having a dual gate structure.
2. Description of the Related Art
An existing DRAM cell device is constructed with one MOS transistor and one cell capacitor. Recently, as a degree of integration in a DRAM is increasingly required, a size of a cell device needs to be reduced, and a size of a cell capacitor needs to be reduced. Such a miniaturization of the cell device and the cell capacitor in the MOS device requires very difficult manufacturing processes. Recently, MOS devices having a floating body have been as DRAM cell devices. In the devices, DRAM memory operations may be performed by storing or removing charges in the floating body. In this technology, since one MOS cell device is used, the DRAM can be implemented by using simple processes unlike the conventional DRAM. Such a DRAM cell device is referred to as a 1T floating-body DRAM cell device (hereinafter, simply referred to as a 1T DRAM cell device or a 1T-DRAM cell device). The 1T DRAM cell device can be adapted to an existing DRAM. In addition, the 1T DRAM cell device can be embedded in an existing logic circuit (for example, a micro-processor or a network-processor). In this case, the 1T DRAM cell device is called as an eDRAM cell device. The 1T DRAM cell device used in the eDRAM has a high memory capacity or a high operating speed, so that its applications are increased. The 1T DRAM cell device has a floating body. The adjacent floating bodies are electrically isolated from each other so as to be floated. Information is stored in the floating body. Therefore, unlike a conventional DRAM cell device, in the 1T DRAM cell device, no cell capacitor is required. As a result, a cell area can be reduced, and a degree of integration of the DRAM cell devices can be improved.
FIG. 1A shows a conventional 1T DRAM cell device which is implemented on an SOI (Silicon On Insulator) substrate. The SOI substrate is a single-crystalline silicon film where a substrate 1, a buried insulating layer 2, a source 8, a drain 9, and a floating body 3 are formed. The source 8 and the drain 9 are disposed at both sides of the floating body 3. A gate insulating layer 10 is formed on the silicon film, and a gate electrode 11 is disposed on the gate insulating layer.
FIG. 1B shows a conventional 1T DRAM cell device. The DRAM cell device has a lower gate electrode 21 being formed in the fifth insulating layer 20 and the fifth insulating layer 20 is formed on the substrate 1. The source 8 and the drain 9 are disposed at both sides of the floating body 3, and a gate insulating layer 10 and a gate electrode 11 are formed on the silicon film.
Next, the operation bias condition of the conventional one-transistor DRAM cell in FIG. 1 is described in FIG. 2. The operation method for the 1T DRAM cell device is disclosed in U.S. Pat. No. 7,239,549. The write1 operation due to the collision ionization method is described in FIG. 2A and the write1 operation due to the GIDL (Gate Induced Drain Leakage) in FIG. 2B.
Since the miniaturization of device leads to an increase in capacity of DRAM, it is very important. However, due to the miniaturization of channel length, a short channel effect occurs. In addition, a size of a floating body which stores information is reduced, so that a difference in drain current between the write1 state and the write0 state is decreased. Accordingly, it is difficult to sense and to store information for a long time.
In order to solve the problem, 1T DRAM cell devices having a double-gate structure that is effective in the miniaturization of device have been proposed. Hereinafter, the representative structure among the proposed double-gate structures will be described in detail.
FIG. 1B shows an example of a conventional 1T DRAM cell device published in UC Berkeley (Charles Kuo et al, “A Capacitor-less Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications,” IEEE Trans. on Electron Devices, vol. 50, no. 12, pp. 2408-2416, 2003). In the example, an upper gate 11 and a lower gate 21 are disposed on and under a floating body 3, respectively, so that the upper gate 11 and the lower gate 25 are electrically independent of each other. In the 1T DRAM cell device, due to the characteristics of the double-gate structure, it is possible to suppress the short channel effect and to improve the sensing margin. In the cell device, a negative voltage (for example, −1 V) is applied to the lower gate 25, so that the holes can be held in the floating body 3 in the write1 operation for a long time. In addition, during the write0 operation, a voltage of 0 V is applied to the lower gate 25, so that the holes in the floating body 3 can be effectively flown into a drain region. Accordingly, it is possible to improve the sensing margin. However, the 1T DRAM cell device has the problems as follows. Generally, in a case where the floating body 3 in the double-gate structure has a small thickness and is completed depleted, a width of the body needs to be small so as to suppress the short channel effect. A threshold voltage of the double-gate device having a fully depleted body depends on the thickness of the body and a doping concentration of the body. Although a fully depleted device is actually manufactured, a dispersion of the threshold voltages among the cell devices is too large, so that it is difficult to implement a practical device. In addition, the lower gate electrode 25 needs to be independently provided to each cell device, there is a problem in that a degree of integration of cell devices is greatly decreased in a layout of a cell array of the cell devices.
An example of a structure for solving the above-described problems is disclosed in Korean Patent Application No. 2007-0086516. Since this device structure includes a dual gate structure as described above, it is advantageous for reduction in size. The principal characteristic of this device structure lies in the fact that a gate stack (a tunneling insulating layer, a storage node, and a blocking insulating layer) for storing electric charges and a control electrode are formed on either side of a floating body, thereby enabling a non-volatile function without decreasing the degree of integration. This Korean patent is configured to reduce the characteristic distribution of a device, which may be generated when a fully depleted thin body indispensable for reduction in size is employed, using the non-volatile function. This Korean patent claims examples of a structure and a fabrication method. Accordingly, the present invention provides a device structure with a focus on a variety of operation methods that can be used when the above-described device is applied as a 1T-DRAM cell device.